The present invention relates to a flip-flop circuit and, more particularly, to a flip-flop circuit having a short signal propagation delay time.
FIG. 1 shows a static flip-flop circuit according to a conventional technique. In FIG. 1, the flip-flop circuit is constituted by two inverters 21 and 22, and two switches 23 and 24. In this flip-flop circuit, the switch 23 is operated in response to an input to a latch input terminal 26 to read a signal at a data input terminal 25, and the switch 24 is operated in response to an input to a hold input terminal 27 to hold the data.
FIG. 2 shows the operation of the circuit shown in FIG. 1. Since the flip-flop circuit in FIG. 1 performs a static operation by holding the data using the two inverters 21 and 22, delay times TD1 and TD2 of the two inverters are added to switching operation time, thereby increasing a total delay time, as shown in a timing chart in FIG. 2.
FIG. 3 shows a dynamic flip-flop circuit as another conventional example. Referring to FIG. 3, the flip-flop circuit is constituted by an inverter 31 and a switch 32. In the flip-flop circuit, the switch 32 is operated in response to an input to a latch input terminal 35 to read a signal at a data input terminal 34, and information is held by a capacitor 37 connected to the input of the inverter 31. The held information is then held by the next flip-flop circuit by a switch 33 operated in response to an input to an input terminal 36.
A total delay time of the flip-flop circuit having the above arrangement is determined by a delay time of the inverter 31. However, a loss of information may occur at a low frequency eecause the information held by capacitor 37 is discharged at the low frequency. Accordingly, operation at a low frequency cannot be performed.